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Memory Reduction of Stateful Network Traffic Processing
Hlaváček, Martin ; Puš, Viktor (referee) ; Kořenek, Jan (advisor)
This master thesis deals with the problems of memory reduction in the stateful network traffic processing. Its goal is to explore new possibilities of memory reduction during network processing. As an introduction this thesis provides motivation and reasons for need to search new method for the memory reduction. In the following part there are theoretical analyses of NetFlow technology and two basic methods which can in principle reduce memory demands of stateful processing. Later on, there is described the design and implementation of solution which contains the application of these two methods to NetFlow architecture. The final part of this work summarizes the main properties of this solution during interaction with real data.
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Applied use of DSP blocks in Intel FPGA
Kondys, Daniel ; Pokorný, Jiří (referee) ; Smékal, David (advisor)
This bachelor's thesis explores the utilization of DSP blocks located particularly on FPGA Stratix 10 DX 2800 for the implementation of a counter and a comparator. In the theoretical part, topics such as the protocol Ethernet, the FPGA technology and its relation with Network Interface Controllers are explained, followed by a~description of general design flow for digital circuits on FPGAs and a detailed insight on DSP blocks in the Virtex UltraScale+ XCVU7P and Stratix 10 DX 2800 FPGAs. The practical part focuses on the design, implementation and testing of the counter and comparator, followed by measurements of their impact on FPGA's resource utilization and maximum frequency. Lastly, it describes the integration of these components into modules that are part of the COMBO-400g1 Network Interface Connector firmware and analyzes their impact on FPGA's resource utilization and maximum frequency.
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Racing Motorcycle On-Board Computer
Dokulil, Marek ; Šimek, Václav (referee) ; Crha, Adam (advisor)
The bachelor work is divided into three main sections. The first section deals with the description of the onboard computers available on the market that can be used on a racing motorcycle. The second part of this work focuses on the possibility of scanning speed engines, primarily gasoline, where the principles are described. In the third part there is described the design of the onboard computer and its construction. After reading the third part, the reader should be able to construct his/her own onboard computer according to that design.
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Frequency measurement module with Xilinx FPGA
Galia, Jan ; Macho, Tomáš (referee) ; Havránek, Zdeněk (advisor)
This thesis deals with designing a frequency measurement module using a programmable logic device. There is also a list of data acquisition cards of several manufacturers. The selected method of direct period measuring is described here including the circuit design of the module. The work also contains a description of FPGA’s firmware and its commands. The PC programme and the measurement results are presented in the end.
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Control of water supply for a house
Chvátal, Michal ; Richter, Miloslav (referee) ; Macho, Tomáš (advisor)
The diploma thesis deals with the design and implementation of the system that will control the water supply for the family house and its garden. The system aslo allows you to store a history that can be viewed via the web interface. The web interface also allows you to set system parameters and monitor the current status.
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Control of water supply for a house
Chvátal, Michal ; Richter, Miloslav (referee) ; Macho, Tomáš (advisor)
The diploma thesis deals with the design and implementation of the system that will control the water supply for the family house and its garden. The system aslo allows you to store a history that can be viewed via the web interface. The web interface also allows you to set system parameters and monitor the current status.
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Applied use of DSP blocks in Intel FPGA
Kondys, Daniel ; Pokorný, Jiří (referee) ; Smékal, David (advisor)
This bachelor's thesis explores the utilization of DSP blocks located particularly on FPGA Stratix 10 DX 2800 for the implementation of a counter and a comparator. In the theoretical part, topics such as the protocol Ethernet, the FPGA technology and its relation with Network Interface Controllers are explained, followed by a~description of general design flow for digital circuits on FPGAs and a detailed insight on DSP blocks in the Virtex UltraScale+ XCVU7P and Stratix 10 DX 2800 FPGAs. The practical part focuses on the design, implementation and testing of the counter and comparator, followed by measurements of their impact on FPGA's resource utilization and maximum frequency. Lastly, it describes the integration of these components into modules that are part of the COMBO-400g1 Network Interface Connector firmware and analyzes their impact on FPGA's resource utilization and maximum frequency.
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